1. Field of the Invention
The present invention relates to a semiconductor memory module wherein semiconductor chips are mounted on a module substrate.
2. Description of the Background Art
A semiconductor memory device is, in many cases, utilized in a personal computer, a workstation or the like. In addition, in recent personal computers speed has been increased, density has been increased and performance has been enhanced and, therefore, further increase in memory capacity of semiconductor memory modules is required. In addition, there is an expanding market demand for low cost memories. Therefore, a further increase in the capacity of, and a lowering in the cost of, semiconductor memory devices have come to be required.
The amount of utilization of DRAMs (Dynamic Random Access Memories) for personal computers and the like has increased from among the above described semiconductor memory devices because of the advantage from the point of view of cost per unit bit. Even in the case that the capacity of a DRAM is increased, the cost per unit bit can be reduced by increasing the diameter of wafer for DRAMs. Therefore, DRAMs are frequency utilized.
Even in the case of a DRAM, however, the test period of time and test cost accompanying the increase in capacity have increased and the development costs accompanying improvements in microscope processing technology and costs for increasingly sophisticated facilities have greatly increased and, therefore, the question arises of whether or not these costs can be reduced.
In general, there are three types of bit configurations, four bit, eight bit and sixteen bit, of the input/output of a DRAM, so that the number of types of bit configurations is small. Therefore, in general, one module made up of a plurality of DRAMs is utilized. Semiconductor memory devices such as DRAMs are, in many cases, utilized in module conditions, as described above.
FIGS. 25 and 26 show an example of a semiconductor memory module according to a prior art. The semiconductor memory module according to a prior art has a structure wherein a single chip 117 having a bare chip 101, a die pad 104, bonding wires 105 and a lead frame 110 sealed in mold resin 108 is mounted on a module substrate 102, such as of an SOP (Small Outline Package) and of a TSOP (Thin Small Outline Package), corresponding to a surface mounting technology wherein parts can be mounted on both surfaces of a printed circuit board. In addition, data input/output terminals DQ0 to DQ63, for inputting/outputting signals connected to lead frames 110 of single chips 117, are provided on module substrate 102.
In addition, a basic trend of developing thinner and more miniaturized memory packages has been progressing, together with the enhancement of performance and functions of memory chips. Thus, package modes have greatly changed such that in addition to the insertion system that has been previously adopted for memory packages, in recent years a surface mounting system has been adopted.
At present, the surface mounting system has become the main trend, as opposed to the insertion system, and further reduction in size and in weight of packages is greatly required. Simplification of design, increase in reliability and reduction in cost has been achieved up to the present by utilizing semiconductor memory modules.
In addition, in the case that a defective chip is discovered in a module test after the manufacture of a semiconductor memory module, testing and replacement of defective chips are repeatedly carried out until defects are no longer found in the manufacturing process of a semiconductor memory module according to a prior art.
In general, a DRAM is provided with an internal voltage generation circuit for generating a predetermined internal voltage utilizing a power supply voltage VDD supplied from the outside. The internal voltage generation circuit is, for example, a word line driving voltage VPP generation circuit, a reference voltage VREFD generation circuit for a VPP generation circuit, a sense amplifier power supply voltage VDDS generation circuit within a memory array, a reference voltage VREFS generation circuit for a VDDS generation circuit, a cell plate voltage VCP generation circuit, a bit line voltage VBL generation circuit, a substrate bias voltage VBB generation circuit or the like.
A method is used for controlling the above described internal voltage generation circuit by converting a DRAM to a variety of test modes for a short period of time in order to detect whether or not the DRAM is defective for tests at the time of delivery of the DRAM. According to this method, it becomes possible for a DRAM to forcefully apply a predetermined voltage to an internal circuit. Here, a predetermined voltage is generated in an internal voltage generation circuit by applying a voltage to the internal voltage generation circuit from the outside. This predetermined voltage generated in the internal voltage generation circuit is applied to the internal circuit. Hereinafter the expression xe2x80x9ca voltage is forcedxe2x80x9d is used to indicate xe2x80x9ca voltage is forcefully applied to an internal circuit.xe2x80x9d
FIGS. 27 to 29 are diagrams for describing a semiconductor memory module according to a prior art, on which is mounted a synchronous DRAM (hereinafter referred to as xe2x80x9cSDRAMxe2x80x9d), which is an example of a single chip 117, that can be converted to a test mode before it is mounted on a module substrate 102 so that a voltage generated by an internal voltage generation circuit is controlled.
In the following, a method for controlling an internal voltage generated by an internal voltage generation circuit of an SDRAM, from the outside of the SDRAM, before the SDRAM is mounted on module substrate 102 is described in reference to FIGS. 27 to 29.
FIG. 27 is a diagram shown an enlarged view of one single chip 117 from among a plurality of single chips 117 in the semiconductor memory module shown in FIG. 25. Here, single chip 117 of FIG. 27 is shown as a schematic sketch so that the structure within mold resin 108 can be seen. In addition, a lead frame 110 is electrically connected to bonding pads 106 via bonding wires 105.
In addition, FIG. 28 is a diagram schematically showing the internal structure of a bare chip 101. A test mode detection circuit 150, shown in FIG. 28, generates a control signal for controlling an internal voltage generation circuit and an internal voltage force circuit. The two-stage procedure shown in the following is required in order to enter into individual test modes in order to control the internal voltages generated by a variety internal voltage generation circuits.
First, as a first stage shown in FIG. 29, commands inputted to a chip selection terminal/CS, a row address strobe terminal/RAS, a column address strobe terminal/CAS and a write enabling terminal/WE, provided in a single chip 117 as shown in FIG. 27, are converted to mode register set (hereinafter referred to as xe2x80x9cMRSxe2x80x9d) commands, that is to say, /CS=L, /RAS=L, /CAS=L and /WE=L are attained. In addition, commands inputted to bank address selection signal input terminals BA0, BA1 and an address signal input terminal A7 are set at BA0=H, BA1=H and A7=H. Thereby, single chip 117 enters into a test mode.
After that, as a second stage, the above described MRS commands are again inputted to a chip selection terminal/CS provided in single chip 117, to row address strobe terminal/RAS, to column address strobe terminal/CAS and to write enabling terminal/WE. Thereby, individual test modes determined in accordance with the types of commands inputted to band address selection signal input terminals BA0 and BA1 as well as to address signal input terminals A0 to An are entered. Here, Table 1 shows types of commands for entering a variety of voltage force modes.
Next, the operation of the circuit inside of bare chip 101 that has entered a predetermined test mode according to the procedure of the above described second stage is described in reference to FIG. 28. Signals outputted from a test mode detection circuit 150 in test modes include a test mode VREFD force indication signal TMREFDFRC indicating entry into a variety of test modes, a test mode VREFS force indication signal TMREFSFRC, a test mode VBB force indication signal TMVBBFRC, a test mode VCP force indication signal TMVCPFRC and a test mode VBL force indication signal TMVBLFRC.
A test mode VREFD force indication signal TMVREFDFRC, a test mode VREFS force indication signal TMREFSFRC, a test mode VCP force indication signal TMVCPFRC and a test mode VBL force indication signal TMVBLFRC are transmitted to an internal voltage force circuit 155. A test mode VBB force indication signal TMVBBFRC is transmitted to an internal voltage force circuit 158.
Furthermore, a test mode VREFD force indication signal TMVREFDFRC is transmitted to a reference voltage VREFD generation circuit 151. A test mode VREFS force indication signal TMVREFSFRC is transmitted to a reference voltage VREFS generation circuit 153. A test mode VBB force indication signal TMVBBFRC is transmitted to a substrate voltage VBB generation circuit 159. A test mode VCP force indication signal TMVCPFRC is transmitted to a cell plate voltage VCP generation circuit 156. A test mode VBL force indication signal TMVBLFRC is transmitted to a bit line voltage VBL generation circuit 157.
As shown in FIG. 28, a desired voltage is applied to a terminal DQM, whereby a voltage generated by internal voltage force circuit 155 is forced into a node VREFD, a node VREFS, a node VCP and a node VBL. On the other hand, a voltage is applied to chip selection terminal/CS, whereby a voltage generated by internal voltage force circuit 158 is forced into node VBB. Accordingly, a voltage generated by internal voltage generation circuits 155 and 158, respectively, to which nodes VPP, VDD, VCP, VBL and VBB, respectively, are connected, is forced into internal circuits 161 to 165 connected to the above nodes, respectively.
As shown in FIG. 27, however, the above described semiconductor memory module according to the prior art has a structure wherein bonding pads 106 provided on bare chip 101 and lead frame 110 are connected with bonding wires 105. In addition, in order to force internal voltages VCP, VBL, VBB, VPP, VDDS, VREFS and VREFD from the outside to internal circuits 161 to 165, the voltages are applied to bonding pads 106 provided on bare chip 101 shown in FIG. 27. In general, in wafer testing predetermined voltages are applied to bonding pads 106, whereby a variety of tests can be carried out on the internal circuits of bare chip 101.
These bonding pads 106, however, are not connected to lead frame 110 at the time of assembly. Therefore, voltages cannot be forced from the outside to internal circuits 161 to 165 after bare chip 101 has been covered with mold resin 108 so as to form single chip 117.
Accordingly, after the MRS commands have been inputted to test mode detection circuit 150 in order to enter into individual test modes, as described above, the internal voltages generated in internal voltage force circuits 155 and 158 are forced into internal circuits 161 to 165 by applying predetermined voltages to terminal DQM and to chip selection terminal/CS.
However, the following problems arise in the semiconductor memory module wherein a plurality of single chips 117 is mounted on mold substrate 102.
As described above a plurality of single chips 117 is mounted on module substrate 2 in the semiconductor memory module. In the case that a test is carried out on internal circuits 161 to 165 within single chips 117 after singles chips 117 have been mounted on this module substrate 2, a signal is inputted to terminal DQM provided on module substrate 2. As shown in FIG. 28, however, a buffer circuit 300 for the formation of an input waveform, in some cases, exists between terminal DQM of module substrate 102 and terminal DQM (chip) of a single chip 117 that becomes the test object.
In addition, control signals and address signals except for control signals inputted/outputted using data input/output terminals DQ0 to DQ71 of the module are all inputted via buffer circuit 300 in a product called registered DIMM of an SDRAM module. Accordingly, voltages generated by internal voltage force circuits 155 and 158 cannot be applied to internal circuits 161 to 165 of the SDRAM after converting a single 117 to a test mode by applying a predetermined voltage to terminal DQM or to chip selection terminal/CS after single chips 117 have been mounted on module substrate 2.
Furthermore, in the case that a system test is carried out on the semiconductor memory module under the condition wherein single chips 117 have been mounted on module substrate 102, the voltages applied to respective input terminals DQ0 to DQ63 of module substrate 102 shown in FIG. 25 are voltages specific to this system test. Therefore, a desired voltage cannot be applied to a specific input terminal of a single chip 117.
In addition, it is necessary to input predetermined commands, such as MRS commands, to a single chip 117 in order to enter into individual test modes. However, in many cases, it is extremely difficult to follow, under actual usage conditions, the predetermined procedure required for test mode entry according to the usage of a memory controller of the system.
Unless a test for detecting whether or not there is a defect among single chips 117 can be carried out after single chips 117 have been mounted on module substrate 102 as described above, the semiconductor memory module cannot be repaired according to a technique wherein a defective single chip 117 is detected so that defective single chip 117 is replaced with a repair chip that properly functions.
An object of the present invention is to provide a semiconductor memory module capable of performing a test for a semiconductor chip after the semiconductor chip is mounted on a module substrate.
A semiconductor memory module according to the present invention is a semiconductor memory module having a plurality of units of the same type as the following mounted on a module substrate. The unit has a semiconductor chip having an internal voltage generation circuit for internally generating a voltage utilized in an internal circuit, and a voltage application terminal, electrically connected to the internal circuit, for allowing a desired voltage to be applied to the internal circuit using a device for voltage application located outside of the plurality of semiconductor chips. In addition, the internal voltage generation circuit and the voltage application terminal are electrically connected by a conductive member.
According to the above described configuration, a variety of tests can be carried out by applying a desired voltage to the internal circuit after the semiconductor chips are mounted on the module substrate.
A semiconductor memory module according to another aspect of the present invention is a semiconductor memory module having a plurality of units of the same type as the following mounted on a module substrate.
The unit has an internal voltage generation circuit, provided inside of a semiconductor chip, for internally generating a voltage utilized in an internal circuit of this semiconductor chip, and a terminal for command input, provided outside of this semiconductor chip, to which a test mode command is inputted for indicating that a test is to be carried out on the semiconductor chips in the semiconductor memory module.
In addition, the unit has a test mode detection circuit, provided inside of the semiconductor chip, for outputting a test mode indication signal in the case that a test mode command is inputted to the command input terminal, and an internal voltage force circuit, provided inside of the semiconductor chip, for applying a voltage to the internal circuit when a test mode indication signal outputted by the test mode detection circuit is inputted.
According to the above described configuration, a variety of tests can be carried out by applying a voltage generated by the internal voltage force circuit to an internal circuit after the semiconductor chips are mounted on the module substrate.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.